What does it take for one of the world's most complex engineering organisations to commit — fully — to 3D IC as a strategic direction? And what does that commitment reveal about the gaps the entire industry still needs to close?

What you’ll learn...

(02:07) Sujit's background: 30+ years in semiconductor processing and packaging, 300+ patents across X-ray lithography, CMP, and advanced thin film

(02:07) The three vectors driving Intel's 3D IC strategy: reticle size limits, AI/HPC memory bandwidth demands, and chiplet cost efficiency

(04:33) EMIB for 2.5D lateral die-to-die interconnects, and Foveros / Foveros Direct for 3D vertical copper-to-copper hybrid bonding

(06:48) Tackling design partitioning, thermal management, power delivery, and testability through STCO — System Technology Co-Optimization

(09:45) The biggest ecosystem challenge: breaking down cultural silos between silicon, package, and board design teams

(13:10) Why showing engineers real co-design data was the decisive factor in driving the mindset shift

(14:33) The EDA gaps still needing breakthroughs: full-stack digital twin, integrated multi-physics simulation, and cloud-based collaboration

(17:50) Killer app segments: AI and HPC, autonomous driving, communications bandwidth, and AI-driven EDA automation

(20:16) What the 3D IC era demands of engineers: T-shaped skills, cross-domain awareness, and real-world trade-off thinking

(24:57) Sujit's call to action: shift from tool-centric to system-level thinking, build the digital twin, standardise data exchange

More about this episode...

In this episode of the Siemens 3D IC Podcast, host Tova Levy speaks with Sujit Sharan, Intel Fellow in the Advanced Packaging Technology & Manufacturing Organization at Intel Corporation. With over 30 years in semiconductor processing and packaging and more than 300 issued patents, Sujit is one of the industry's foremost voices on making 3D IC real at production scale.

Three forces drive Intel's 3D IC strategy: reticle size limits on monolithic die; AI and HPC bandwidth demands requiring memory physically close to compute; and the cost efficiency of chiplet disaggregation. Intel's response is EMIB (Embedded Multi-die Interconnect Bridge) for lateral 2.5D die-to-die and die-to-HBM connections, and Foveros / Foveros Direct for vertical 3D stacking via copper-to-copper hybrid bonding — complementary technologies, not competing ones.

Managing this complexity means abandoning the silo model. Sujit's answer is STCO — System Technology Co-Optimization — treating silicon, package, and board as one integrated system. Cultural resistance was real; the solution was data, showing engineers the measurable gains co-design actually delivers.

The ultimate EDA goal is a full-stack digital twin spanning electrical, thermal, and thermomechanical analysis with near-real-time feedback. Siemens' Innovator 3D IC is a step in that direction, but standardised data exchange and cloud-based collaboration remain critical gaps. Sujit's call to action: EDA partners must shift from tool-centric to system-level thinking — and the whole industry needs to move together.

Ideal for: 3D IC architects, silicon IP designers, advanced packaging engineers, chiplet ecosystem participants, EDA users, and anyone navigating the shift from monolithic SoC design to heterogeneous, disaggregated integration.

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