What does it take to build a chip when the chip itself is an ecosystem — and the wire connecting everything has become the biggest bottleneck in modern semiconductors?

What you’ll learn...

(00:56) Bob's background and the founding of NHanced Semiconductors

(01:17) What "foundry agnostic" really means — and why trust matters

(03:16) How advanced packaging became a front-and-center design discipline

(04:30) Why wire — not transistors — now dominates power and delay

(06:46) The ecosystem village: EDA vendors, foundries, and test houses

(09:05) NHanced's collaboration with Siemens and Calibre 3D

(11:09) Making 3D IC accessible: MPWs, chiplets, and lower barriers to entry

(15:00) DFM advice: test planning, wire length, and stakeholder alignment

(18:30) Three to five years out: chiplets, photonics, and targeted designs

(23:05) Bob's message to the ecosystem: invest in the ADK/PDK flow

More about this episode...

In this episode of the Siemens 3D IC Podcast, host Tova Levy speaks with Bob Patti, President and CEO of NHanced Semiconductors, about what it takes to build and scale advanced packaging — and why the wire, not the transistor, has become the defining challenge of modern chip design.

Bob opens by explaining what makes NHhanced's foundry-agnostic model work: the company operates like a CMOS fab but builds no transistors, positioning it as a trusted neutral partner rather than a competitor to the foundries it works with. That neutrality is what allows NHanced to take material from virtually every major fab in the world and integrate it into complex 2.5D and 3D packages.

He then makes the case for why advanced packaging has moved from a backend afterthought to a front-and-center discipline. As transistors have scaled, wiring has gotten worse — now accounting for roughly 95% of the power and delay in modern circuitry. Advanced packaging attacks that problem directly, reducing wire length by orders of magnitude and enabling power reductions of up to 1000x in die-to-die interconnects. Achieving this requires the full ecosystem: EDA vendors, foundries, OSATs, and test houses collaborating from day one — with Siemens and Calibre 3D called out specifically for leading ADK development and making advanced packaging accessible to designers who aren't packaging specialists.

The episode closes with a look ahead: in the next three to five years, Bob sees a broader chiplet market, more off-the-shelf high-performance components including GaN and photonics, and a return to targeted, application-specific design — only now powered by heterogeneous integration.

Ideal for: 3D IC architects, advanced packaging engineers, chiplet ecosystem participants, EDA users, semiconductor startup founders, and anyone navigating the transition from monolithic SoC design to heterogeneous integration.

Connect with Tova Levy

Website

Connect with Bob Patti

NHanced Semiconductors Website