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TSMC is working hard to build new fabs in just Taiwan. There are simultaneous builds in three cities, Fab 20 in Baosan, Hsinchu with four phases. One of those is now done. Fab 22 in Nanzi Kaohsiung has five phases planned, one done, two with shells up and moving in equipment. And then there's Fab 25 in Taichung. This site is just dirt right now, but I expect it to go fast. Not to mention the massive advanced packaging fabs. My favorite one, AP7 is down in Jiayi, next to the Southern branch of the National Palace Museum. TSMC has allocated over $60 billion of capital expenditure in 2026 to build these fabs. Yet AI demand so far has been insatiable and customers like Nvidia want their chips now. But the hard truth, one mentioned by top management like CCWEI is that capital expenditures spent in 2026 will not hit the market until 2028. Maybe a bit earlier. Does that mean that the AI boom is now on pause? Not quite. TSMC has a trick up its sleeve. Cross node utilization in today's rather meandering video what a fleet of little trucks has to do with the AI boom. One of the worst kept secrets in semiconductor manufacturing is that logic process node names mean nothing. One of the most underrated secrets in semiconductor manufacturing is that everything in the node is iterative. But let me get back to that later. Let me first explain a process node Recall a long time ago when I did a video about design technology co optimization. Advanced nodes are manufacturing lines crafted in partnership with the customer. My general understanding is that when TSMC starts on a node, the R and D guys bring together a collection of technologies to the business development people. A package is selected, curated and sold to the customer, priced accordingly. Advanced nodes being so customized now is partially why TSMC's node roadmap starts looking like ASCII art. It's not a smooth n3 to n2 to a14 transition. It's more like n3 to n3e, n3p, n3x n3c, while n2 splinters into n2p, n2x n a16 so on. The node is then put into the fab, but it's not done yet. Inside the fab, the manufacturing team will continue working on the node, running experiments to squeeze improvements in yield point by point, and over the months the yield improves to something like the mid-80s percent. The fab manufacturing guys are good at their job. Someone once whimsically mused to me that they are far overqualified for their positions because oftentimes the manufacturing guys discover enough improvements that the managers might decide to repackage and rebrand the node as something new. That is basically the story of TSMC's N6 node which was birthed out of N7. Or they might even hold back a set of discovered improvements, reserving it for a future node. So in the end, what is a process node really? A fab has a collection of tools. The wafer is carried around the fab, visiting tools and being treated by said tools per a preset recipe. I'm for sure skipping over a bunch of detail, but imagine it as like that. The general impression of TSMC's modus operandi is that they build whole new fabs or fab phases for brand new process nodes. For example, Fab 15 in Taichung, which sits on a frequent mountain, was built for the N7 process node and the N5 node gets a brand new fab in Tai 9, the monstrous size fab 18. This is in contrast to other large semiconductor companies like intel, which tends to build one big fab or shell which they then over time either fill up the space or upgrade with new tools as the products advance in node process. There are a few perceived reasons behind this difference of style. Intel has no real need for a 45nm CPU in 2025. TSMC's fabs, on the other hand, might be for clients who in theory can buy the same chips for an extended period of time. There is also an accounting thing. One of a fab's largest costs is depreciation, a non cash charge representing a tool's useful life. So after a few years, maybe five to seven, the fab becomes fully depreciated and their revenue becomes all profit in theory though in reality tools break and need maintenance all the time. Depreciation is a real expense and this is why Charlie munger calls EBITDA BS earnings. One of the challenges with TSMC's perceived modus operandi is what happens when big customers move up in the node chain. Imagine a massive customer like Apple. Their iPhone chips drive so much volume that TSMC might have to build a whole new fab to accommodate them. If they ship their production from the N7 to the N5 nodes, those volumes leave the Taichung fab for the Tainan fab. And this leaves the TSMC manager in charge of that Taichung fab with an Apple sized hole in their production volumes that they now have to fill. This can strand a fab. Here's what I mean. Like right now N2 is too new and immature for most customers to adopt. It is also kind of weird since it uses the new gate all around transistor. But those customers are coming soon. N3 is the sweet spot between newness and performance and what all the biggest customers like Nvidia are right now using. The chips in Nvidia's latest Varrubin platform run on N3. N4 might be older but is well established and still very leading edge. Lots of high performance compute customers are going to use it like I imagine some of those AI accelerator startups will use N4 to start. Then how about N7? N6? That one's tough because on one hand it is now almost 10 years old and quite far from the leading edge. The gap between N7 and N3 is significant enough that you'll probably want the latter. But on the other hand, N7 is expensive and complex for trailing edge customers who are going to prefer a cheaper, more mature node like 28nm which uses a planar transistor design. Now the N7 node is caught in no man's land. This is why intel upgrades their fabs over time to the latest node. You need customers to keep the FAB fully utilized and one of TSMC's major challenges in the pre AI boom era was a dwindling number of leading edge customers. If the utilization ratio drops too far, maybe to 60 to 70% then that fab loses money. If the market does not turn around then the fab potentially doesn't make back its money and becomes a stranded investment. TSMC suffered this a little bit in early 2023 when the post Covid chip bust hit the mobile industry pretty badly and their N7 fabs in Taichung dropped under 70% utilization. OK, remember that I said that process nodes are iterative. Semiconductors are built up in layers. At the bottom layer you might have something like the transistors. One layer above them there are the layers of copper or aluminium interconnects called metal layers. These are the fine metal wires that carry power or data signals across the chip and are laid down in a stage called the back end of the line. The smallest finest wires are at the bottom metal layers which we might call M1 or M2. In the N5 node these M1 wires might be about 28-30nm from center to center. As the metal layers get higher, the interconnects get wider. So at the highest metal layer you might get interconnects about 1.5 or even 3 micrometers wide. This is a structure shared by all the nodes. And what this means is that the N16, N10, N7, N6, N5, N4 and N3 process nodes might have a whole lot of process depths in common, like the stuff at the critical transistor layers will for sure be quite different. But much of everything else above those transistors, let's say maybe the M4 to M15 layers might be similar or even the same. This is why fabs still use a lot of older duv machines a lot. It's for these higher layers. For at least the past 10 years, TSMC has leveraged this layer overlap to avoid fab strandings. Back in 2015, TSMC's then co CEO Mark Liu mentioned in an analyst conference call that their 20nm and 16nm nodes have 95% tool overlap. His point being that if a customer decides they want to move up to the 16nm node, the capacity can be made available for them without building new nodes by converting existing 20 nanometer capacity a few years later. In 2018, the other TSMC co CEO Cici Wei mentioned in a conference call that their N10, N7 and N7 nodes have 90% tool overlap, and this again can be used to accommodate a rising customer. In case you're wondering, N7 is a modified version of N7 but includes one EUV layer. It's well known as TSMC's first taste of EUV, a custom node made for Huawei. CFO Laura Ho added that the tool overlap from N7 to N5 would again be more than 90%. The point being that TSMC can avoid fab strandings by managing N10, N7 and N5 as a single massive pool of capacity. This way, TSMC can upgrade fabs to newer nodes over time as customers progress without having to build a whole new fabric. And the old fab doesn't get stranded. It's not free, but it does save on capital expenditure, which matters when these fabs cost billions of dollars. Now, with the AI boom, TSMC faces a problem unlike any other in its history. It needs so much more advanced capacity. In particular, they need a lot of N3 capacity, and fortunately there's a 90% tool overlap with N5. So in 2024, TSMC management explained in a conference call that they're converting N5 capacity to N3, paying a cost to do so in terms of a gross margin hit. In the Q1 2024 conference call, CCWEI was asked whether they can convert some of their N7 capacity over to N3 in the same way as they are doing with N5. Recall at the time that N7 was not doing that well in the wake of the post Covid smartphone and PC decline, Wei responded that that would be far harder. TSMC's N5 and N3 nodes have more overlap and moreover both nodes are housed inside the same fab. Tainan's Fab 18. There's a massive wafer bridge you can see connecting the various phases, and this makes the conversion that much easier. By contrast, N7 is all the way in Taichung, maybe 100 miles away as the crow flies, and Wei seemed enthusiastic that N7 capacity would be coming back anyway, so things were fine. About a year later, his tune changes in early 2025, Wei says that they have to convert N5 capacity to N3 to accommodate future AI products, read Vera Rubin. Yet at the same time N5 is still in high demand, so finding the right opportunity to switch over is tricky. But now in early 2025, CCWEI mentioned that they figured out a way to use N7 capacity to support N5, which has about 90% tool overlap. Recall, I said that those fabs are about 100 miles apart from one another. How does that work? One of my favorite things about TSMC is how they move their wafers between fabs. After TSMC's wafers come out of their front end fabs like in Hsinchu or Tainan, they need to go to the advanced packaging fabs in Miaoli or Jiayi to do the coas or info or whatever the van's packaging is called. How do they transport those $20,000 or whatever wafers it's with trucks? They take a bunch of foups and put em inside a semi customized truck and then the trucks head on over to the Jiayi or Miaoli fab a few dozen miles away. Just an ordinary truck when first told about this, I found it immensely amusing that there are ordinary looking trucks puttering about on Taiwan's highways and with likely tens of millions of dollars of chip inventory sitting inside. Like what happens if one of them gets into a crash? Will Nvidia miss earnings because of this? TSMC also offers a small wafer shuttle service for quite some time now. Like if a wafer needs to be shipped from the fab to some failure analysis lab and that's done by a simple shipping service provided by a third party logistics company. TSMC's ESG site has a story from 2020 detailing how they improve the logistics and work conditions for the drivers of these freight trucks. It also has a picture of one open so you can see inside. You can guess where I'm going here. The solution TSMC figured out to Cross utilize the N7 and N5 nodes is by massively expanding the trucking service, Fabs and Tainan produce the critical layers of an N3 or N5 wafer and nothing more. Then TSMC sticks those unfinished wafers inside a truck and they drive it 100 miles up the Taichung where an underutilized N7 N6 wafer fab finishes the rest of the wafer. This leaves the Tainan Fab spending all of its time and capacity on critical work. Just regular trucks. How can you ID these trucks? They will have a TSMC logo on them or something like it. Maybe a derivation like a little guy with a chip wafer logo on his belly. I believe this only goes on while TSMC is converting its N5 capacity to N3, buying and installing new tools or whatever. And I reckon if N3 demand remains robust then it will try to convert over its N7 N6 capacity too at some point. Feels like a natural next step. So imagine that the world's largest infrastructure buildout, the foundation of the AI ecosystem is dependent on a fleet of low tech trucks hoofing it on Taiwan's highways. For some reason that amuses me. Now I admit that this is not some groundbreaking piece of news after all, ccwei has been mentioning it on the conference calls for a few years now. But I think it gives you a sense of just how fluid the definition of these process nodes are. Moreover, this cross node utilization is something no other company is capable of and it can only be done in Taiwan. It shows how TSMC can leverage its massive existing foundation of infrastructure to rapidly scale up manufacturing volume like no other company can. Alright everyone, that's it for tonight. Thanks for watching. Subscribe to the channel, Sign up for the Patreon and I'll see you guys next time.