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My back aches as I write this, but can you believe that 2007 was almost 20 years ago? That year the 45 nanometer process node first entered high volume production. It was a long time ago, but still I think it might be worth examining in today's video. Let us together lavishly break down the 45 nanometer process node. Gird your loins folks. This is a big one. But first I want to remind you about the asianometry Patreon and the Early Access tier members. Get to see new videos first and get the references attached. Early Access directly supports the channel and really helps. Thank you and on with the show. And before we begin, I want to thank Kaiko Minakata who produced a fantastic walkthrough. Check out Minakata San's LinkedIn. He has prepared other documents concerning the yield improvement process and it's a treasure trove that you should review. The link is in the description let's begin with the crashiest of crash courses on the mosfet. This acronym stands for Metal Oxide Semiconductor Field Effect Transistor. Like we have spoken before, a A MOSFET has a gate thin layer of gate oxide and two areas of doped silicon called a source and a drain. When enough voltage, the threshold voltage, is applied to the gate, it interacts with the gate oxide and the silicon substrate below to create an electric field. The field then accelerates charge carriers from the source to the drain. That pathway between source and drain is called the channel. Modern logic fabs do CMOS or Complementary Metal Oxide semiconductors. As the name indicates, CMOS pairs in N type MOS and a P type mos transistor pmos. Both transistors largely work the same. The major difference is that one the NMOS transports negatively charged electrons, the other, the pmos, transports positively charged electron holes. The transistors are wired up to metal interconnects embedded in layers on top of them. These layers are called metal layers because the interconnects are metal. The metal wires go down and make electrical connections with the transistor itself at specific points called contacts. It is a significant challenge of device scaling because the contacts shrink with the device. The process node's ultimate goal is to fabricate these very small devices at high volume. The devices must be consistently sized and perform reliably over a long period of time. Deviations can cause the device to perform below par. We can measure this via a metric called parametric yield or the device can outright fail and and that's measured using catastrophic yield. Here I want to note that people have Spent their whole careers studying each of these steps. I'm not going to go into these steps with intense depth. The goal is to keep moving forward so variations abound. We must first check the substrate, as in the silicon wafer, after it arrives from the vendor. And this check has three parts, each for a different thing. To start, we evaluate the concentration of dopants in the silicon. Wafers are made from slices of crystals literally pulled out of a hot silicon melt. Yes, the famous Chokhrowski method. During this pulling process, small impurities like carbon, oxygen and metals can get into and contaminate the melt. If these impurities get incorporated into the transistor, especially metal impurities, then it will cause the transistor's threshold voltage to fluctuate. And then the transistor might not switch when it is supposed to. So we check for impurities by measuring the silicon wafer surface's electrical resistance against the specs. A four point probe is lowered onto the wafer surface and runs a current from one point to another. After that, we need to check the silicon's crystallographic structure. The silicon wafer is what we call a single crystal, meaning that the whole wafer is a continuous unbroken crystal lattice. Any interruptions, stacking, faults or impurities in that crystal lattice can trap or interfere with the charge carriers moving through the silicon. This hurts device performance. So we need to check the silicon's crystallographic orientation. This is done with a machine called an X ray diffractometer or xrd. It hits the wafer with an X ray beam and reviews what reflects back and how strongly if there's scattering. It might be because the lattice has strains or faults. Third, we want to check the substrate surface for bending or any non flatness. Such bowing or warping as it is called, can affect lithography performance later in the process. How? Because advanced lithography machines have extremely tight depths of focus. It is a range where the image of the photomask's pattern remains in focus. So. So the whole substrate must stay within DOF limits. Bowing and warping affects that. Obviously this is commonly done using a tool called the stylus profilometer or profiler. It is like a finger with a very small diamond tip and we drag that across the wafer surface many times back and forth to create a 3D picture. The way it works kind of reminds me of of an atomic force microscope itself. A very cool piece of kit. Non contact methods based on lasers and capacitive sensing do exist, but tend to cost more. Finally, we clean the substrate of organic compounds, oxides and metal impurities. This is particularly important because contaminants left over on the substrate's surface can get trapped under the gate and affect transistor performance. In the early days of semiconductor manufacturing, wafers were cleaned with scrubbing brushes or ultrasonics, as well as baths and horrible chemicals like hydrofluoric acid, aqua regia, or boiling nitric acid. None of this worked very well. Ultrasonics cracked the wafers and relatively dirty chemicals contaminated the wafers too. Ironic. The very act of cleaning, making things dirtier. Sounds like me around the house then. In the 1960s, Werner Kern, then at the American company RCA, introduced a method called RCA clean that is now the gold standard. The core of RCA Clean involves dipping the wafer into two baths for 10 minutes. The first bath, called SC1 in industry parlance, is highly alkaline diluted hydrogen peroxide and ammonium hydroxide. It is mostly for breaking down organic surface films. The wafer is then taken out, washed with ultra pure water, and then dipped into a second acidic bath called SC2. Obviously, this bath is made of diluted hydrogen peroxide and hydrochloric acid and removes metal contaminants. Optional additional steps to RCA Clean are available. And I recommend reading Werner Kern's retrospective of the evolution of silicon cleaning technology. Surprisingly clean Writing after preparing the substrate, we just getting started, baby. We need to electrically isolate the transistors. Good fences make good neighbors, as goes the poet Robert Frost. We must electrically isolate the transistors to keep their currents from leaking and influencing each other. Without this transistor, densities like what we have today are impossible. In the beginning, Fabs used an older method to do this, called local oxidation of silicon. One of silicon's powerful advantages is its oxide silicon dioxide. This process node will use it all over. It is a great insulator and grows on top of bare silicon with just heat and water, kind of like rust on iron. But it will not grow on areas with silicon nitride. So locos, as it's called, electrically isolates the transistors by using silicon nitride as a mask to selectively apply silicon dioxide on top of the silicon substrate. But then emerged an issue with where the silicon dioxide would push into the so called active area where the transistor is. Obviously it should not be there. The shape of this encroachment looks like a bird's beak, so they creatively named it bird's beaking. Bird's beaking also creates bulges and uneven oxide surfaces. These cause problems later at the Lithography exposure stages, bouncing the light at unpredictable angles and destroying uniformity. They used a polishing method known as chemical mechanical polishing, or cmp, to flatten out the bulges. But the first issue, the encroachment, still remained and it finally became untenable at the 250 nanometer node. So the semiconductor fabs adopted a new shallow trench isolation, or sti, sometimes also called the box of isolation technique. STI digs shallow nanoscale trenches between transistors and fills them with insulation. Silicon dioxide in this case. So kind of like moats around castles. Well, the medieval folks didn't fill the moats with silicon dioxide, but you know what I mean. This process begins with growing a very thin 10 nanometer sacrificial layer of silicon dioxide on top of the silicon substrate. Sacrificial means that we will eventually remove this structure much later. In this particular case, the removal is going to happen a long ways away. So just remember anyway, this silicon dioxide layer is grown using a method called thermal oxidation. It basically means to cook the wafer with water at temperatures of some 900 degrees Celsius. Then on top of that, we grow a second layer of silicon nitride between 20 and 50 nanometers thick using low pressure chemical vapor deposition. This layer is a stopping layer to protect the silicon substrate and its delicate crystal structure from a future process step. A stopping layer is basically kind of like a red stop sign that keeps us from etching or polishing away too deep. I just mentioned a while ago what future process depth that this stopping layer is for Chemical mechanical polish. Save that away for later. Once deposited, the layers are checked for thickness using a method called spectroscopy ellipsometry. Light of unknown polarity is shined at the surface and the machine checks what gets reflected back. After this, the lithography is used to pattern where the trenches will be. I covered the whole lithography process flow in prior videos, but let me quickly run through it here. The FAB applies a light sensitive chemical called a photoresist onto the wafer. Then an expensive lithography machine exposes an image of a photomask onto it. The latent image exposure is then developed using a post exposure bake or something like that, depending on the photoresist. After litho, we have etch using the developed photoresist as a guide. A pattern of 700nm to 2 micrometer deep trenches is etched into the silicon nitride, silicon dioxide and silicon substrate layers. We use reactive ion etching, or rie to etch out These trenches in rie, a mixture of volatile etching chemicals, usually based on chlorine and fluorine, is turned into a plasma using a powerful radio frequency field. The plasma is then accelerated at the wafer by an electric field. When it hits the surface, there is a double edge, first physically by the ion bombardment and second via chemical reaction. Progress is measured with another run of that diamond tipped finger stylus profiler. Now we have our shallow trenches. If all good, the photoresist is stripped off. This is done using an oxygen plasma based dry clean method called plasma ashing. The shallow trenches are then lined with a thin layer of silicon dioxide about 5-10nm thick. Grown again with thermal oxidation, it plasters over any damaged silicon in the side walls of the trench and and smooths over the upper parts of the trench for improved electrical properties. The trenches are now dug. Now we need to fill them. This step is called logically enough trench fill and it is performed using a method called TEOS chemical vapor deposition. Basic CVD involves mixing several precursor chemicals in a chamber and then they magically deposit a nanoscale layer of material onto a target. TEOS refers to this specific CVD's precursors, tetraethyl orthosilicate. The wafer is heated to 650 to 750 degrees Celsius and the liquid TEOS is vaporized using a bubbler or a liquid injection system. This TEOS vapor is then introduced into the CVD chamber where it lands on the hot wafer surface and decomposes. This decomposition breaks silicon oxygen carbon bonds inside the teos forming a dense film of silicon dioxide on the silicon. Yes, I know. We just used thermal oxidation to grow a thin layer of silicon dioxide already on the side walls. Why use this complicated TEOS CVD rather than just more thermal oxidation? The reason is because we want the silicon dioxide to get down to the very bottom of the trench and fill it completely and uniformly. This is what the industry called good coverage. And thermal oxidation is not good for that. They want to see the silicon dioxide be huge, solid, thick and tight. Voids, seams and low densities in the trench layers can lead to leakage and yield issues. So TOS CVD after trench fill fabs cook the wafer at temperatures of 1000 degrees Celsius to anneal it. This strengthens the silicon dioxide layer because later steps will use reactive chemicals like hydrofluoric acid and we do not want that eating into the trench. Next is to flatten or planarize the landscape by grinding Any excess silicon dioxide deposited from the TEOS cbd. We need a nice flat surface for future lithography steps and the multi level metal layers that will be stacked on top of it later. This is done using that foreshadowed chemical mechanical polish method. It polishes away about 500 to 700 nanometers of silicon dioxide from the surface with both mechanical grinding and the reactive chemical slurry. Now remember, all the way at the start of this STI flow when we applied a stopping layer of silicon nitride and I said it was going to be useful later. Now it is finally coming into play. It's critical to know exactly when to stop the CMP polish. Let we grind too deep so a laser is shown onto the wafer surface during the polishing sensing for when we finally expose the silicon nitride, our stopping layer. I love plot playoffs like this. Once CMP is completed, the silicon nitride stopping layer has served its purpose and can be removed using a wet etch method, likely hot phosphorous acid. I want to note here that though most documents agree on the general arc of the STI process and others covered in this video, there will be subtle variations between fabs, so your day to day experience may vary. I am also reminding you that this process is being run across the entire wafer. So imagine doing this for billions of transistors and making sure that it is all being done right. Not easy. Okay, the shallow trenches are now done. The fences between the houses have been built. Now let us start preparing the actual transistor's foundations. Starting with the wells. Doing CMOS means creating two different but complementary types of transistors on top of the same silicon substrate. This begins with creating special regions on the silicon with doping. These doped regions on which we build our nmos and pmos transistors are called wells or tubs. My sister's friend has a cat named Tubs. Here he is. When doped with elements like boron, arsenic or phosphorus, the silicon gains new electrical properties. Most fabs will use either boron or phosphorus. Doping with boron creates electron holes or the lack of an electron. Ergo, the silicon becomes positive type or P type. Phosphorus doping adds an extra electron. Ergo, the silicon becomes negative type or N type. You might imagine that the NMOS sits on the N type well and the PMOS on the P type well. It does not. It's the opposite. NMOS sits on P type silicon. PMOS sits on N type silicon. Why? Because. Because when the gate on a MOSFET opens it forms what is called an inversion layer in the channel between the source and the drain. As the name implies, the inversion layer is formed from charge carriers of the opposite charge of the well's doped silicon type example. So an NMOS moves electrons through its channel, right? When a positive gate voltage is applied to the NMOs, the ensuing electric field attracts negative charged electrons up from the silicon substrate to form the inversion layer, bridging the negative charge source and drain. For this to work, the well must be made from positive type silicon. Otherwise we do not get proper field effect control over the semiconductor material. In the old days, doping was done with thermal diffusion, which, which is a fancy name for shoving the wafer into a furnace with the liquid dopant and heating it to 900 to 1200 degrees Celsius. If all goes well, the dopants diffuse into the silicon. Thermal diffusion was later replaced by ion implantation. In it, we energize ions of the dopants and fire them in the form of an ion beam. The dopant ions smash into the silicon atomic structure like little meteorites and implanting themselves. We generally trace the concept of ion implantation to a patent by William shockley filed in 1954. Yes, the same William Shockley who helped discover the first transistor, created the bipolar transistor and was a raging eugenicist. Shockley demonstrated extraordinary foresight with his patent, but he never followed up on the ideas and the rest of the world caught up. The first ion implanters emerged in the 1950s and were just modded ion beam accelerators from nuclear physics labs. Companies then spun off to make commercial versions in the 1970s and 1980s. Ion implantation has remained a critical part of scaling ever since. The idea is simple and the results more deterministic than chemical vapor deposition, which sounds like and probably is literal voodoo, but its process is still technically complex, as we are about to find out. We create the wells for the NMOS first. Remember opposites. So this means creating P type silicon. The ion implantation machine hits the wafer indiscriminately, which is not desired. The ion implantation must fit a specific pattern aligned to where the transistors will be on the chip. Patterning means lithography, and you know what that means. We again slather the wafer with photoresist, expose it in the exposure tool with the photomask, and then develop the exposed image. The mask's image contains holes where the wells will be during image development. The 300 to 800 nanometer thick photoresist layer is Hardened to resist the forthcoming ion implantation, which can be damaging. Now we do the ion implantation and dope the exposed silicon. Boron atoms at a concentration of 10 to 100,000,000,000, per square centimeter are fired at the silicon, embedding themselves a few hundred nanometers inside the lattice. The results are measured with a machine called a secondary ion mass spectrometry, or sims. It bombards the wafer surface with a beam of what are called primary ions. The bombardment causes secondary ions to fly off like chips. The mass spectrometer collects the ions and counts the proportion to verify whether the right proportion of boron ions is embedded inside the silicon. The metrology tool is chosen for its high sensitivity, but as its measuring is destructive, use should be limited. If everything passes, then the photoresist is stripped off using the aforementioned oxygen plasma ashing method that I talked about earlier. Then we do the same process all over again, except this time we make the PMOS's N type C silicon wells. The dopant here is phosphorus rather than boron, but otherwise it's pretty much the same. Finally, remember that thin sacrificial layer of silicon dioxide that we grew with thermal oxidation way long ago? Well, the time has now come to remove that layer because ion implantation is a rough damaging process and hopefully the silicon dioxide took the brunt of the damage. This is done with a simple wet edge. Great. Now we have the 2N type and P type silicon welds that will be the foundations of our complementary PMOs and NMOS transistors. The next thing to do is to build the gate. To give some context, the 45nm node arrived at a pivotal moment in semiconductor history. I covered this in a prior video, so let me move through this first fast. Starting at the 130 nanometer node, Fabs started to notice what are called short channel effects. After many years, the transistor had shrank so much that charge carriers started leaking across into the drain. In response, the semiconductor industry tweaked their recipes. At the 90 nanometer node, they incorporated an altered form of silicon called strained silicon Valley. You'll see it later. I know that sounds ominous. 45nm followed 90, and its major change was in the transistor's gate oxide. To remind you that is a thin oxide layer sandwiched between the gate and channel. It is critical to producing the gate's electric field. Originally, these gate oxides were made from silicon dioxide, but the 45 nanometer node replaces them with a new oxide material, hafnium Oxide, usually hafnium oxides. Higher dielectric constant, or K, helps the gate create a stronger electric field, ameliorating short channel effects, but also necessitates a new process flow. Two pathways emerged, gate first and gate last. Last. IBM championed gate first and intel backed gate last. What follows is the gate last flow, which became the industry standard. It's called that because we produce the real transistor gate at the end. However, we still need a gate to be there to align the source and drain. So we build a sacrificial gate, a dummy gate. Let's do that. To start things off, we clean the wafer surface to remove any residual surface oxide. Basically, you should assume we're cleaning the wafer all the time, really. Next, we stick the wafer into the furnace again to grow a fresh layer of silicon dioxide. With thermal oxidation, the silicon dioxide is also needed as a smoothening layer between the silicon substrate and the hafnium oxide we are about to deposit fabs. Pay a lot of attention to the boundaries between materials, especially here in the channel where charge carriers will be traveling. We want them to go fast and avoid what are called interface traps. Interface traps refer to defects like lattice mismatches or impurities or contamination or dangling silicon bonds, meaning unpaired electrons that can snatch traveling electrons or electron holes. These all can impede charge carrier progress. Pure silicon and hafnium oxide do not match well together. Like incompatible LEGO bricks, there are lattice mismatches. Moreover, the silicon substrate surface will have dangling bonds left over from cleaning or patterning. Growing the silicon dioxide fulfills these dangling bonds, calming them down or passivating them. The amorphous silicon dioxide also acts as a buffer between the silicon and hafnium oxide. Next is to actually deposit the hafnium oxide gate oxide. This must be very thin, literally about 1 or 2 nanometers thick. So we use a special CVD methodology called atomic layer deposition, or ALD to do it. I have covered ALD in prior videos. In its most basic form, it uses alternating reaction and purge half steps to deposit a material layer inside a special ALD chamber. This is different from just throwing them all into the chamber at the same time, which is how traditional CVD does it. So with each 1/10 second cycle, we add layers of about 1 to 2.5 angstroms of high quality hafnium oxide until a layer just a few nanometers has been applied on top of the silicon dioxide buffer to measure the thickness and quality of the hafnium oxide and ensure they remain on spec. There are Two metrology spectroscopic ellipsonometry and X ray refractometry. Spectroscopic ellipsonometry shines a light with a known polarization onto the wafer and examines changes in the polarization after it is reflected back. It is very fast, which makes it suitable for whilst the wafers are on the line, so it checks every wafer. X ray refractometry shines a beam of X rays instead at a very shallow angle. The beams penetrate through the layers and interfere with each other on the reflection path. This interference pattern can tell you the roughness of the silicon surface plus its density. Finally, we can actually build the dummy gate. Unlike the silicon substrate below it, which is made of single crystal silicon, the dummy gate is made from polysilicon, called as such because it is essentially many small silicon crystals separated by grain boundaries. So still more organized than amorphous silicon, which is just a jumble but less strict crystal demands, so we do not have to use Czokrowski to make it. This polysilicon is deposited using CVD again, of course, the variant that we use is called low pressure CVD or lpcvd. I mentioned it earlier and it is one of the older CBD methods out there dating back to 1975. We put a batch of wafers inside a special deposition chamber, long and thin like a hot dog, with heating coils wrapped around them. They heat the wafers to a range of 580 to 650 degrees Celsius at low pressure. Then we pump silane gas into the chamber. Silane is made up of one silicon atom and four hydrogen atoms. When they stick to the hot wafer surface, they decompose. The silicon hydrogen bonds break apart and the hydrogen waves away, leaving behind a polysilicon layer 5-30nm thick. Since the dummy gate is only there to align the source and drain, it will need to be removed later on. To make that easier for us down the line, we lay down another capping layer of silicon nitride using a different variant of lpcvt. Finally, we need to pattern the whole layer to identify where the gates will be and remove the excess polysilicon, leaving behind just the dummy gates. So we do the lithography thing all over again. Applying the photoresist, exposing the wafers to the mask image and then developing the latent image. We etch away the excess polysilicon, silicon nitride and hafnium oxide layers using reactive ion etch. Again, after we strip the photoresist, we are left with a Polysilicon dummy gate stack starting at the top with silicon nitride and going down to the hafnium oxide and silicon dioxide buffer layer. Now we are ready to progress to the next step. The halo. The source and drain processes are a bit Messy here. The 45nm node has us create two things in addition to the source and drain the halo implants and extensions. Let's discuss first the halo implants, also called pocket implants. These were introduced as a measure to suppress aforementioned short channel effects. FAB engineers found that after creating the source and drain ion implanted D dopants were spreading out laterally underneath the gate, shortening the channel even more. Do not want the pocket implants place a heavy dose of dopants in a pocket such to say at an angle underneath the edge of the gate. They use the same dopants of the well underneath the transistor. So if it is an nmos, we inject more P type dopants Boron. Now for the extensions. They are sometimes also called the lightly doped drain source regions. They extend out from the source drain in shallow regions just under the gate. These are meant to protect the gate oxide from what is called hot carrier injection. Charge carriers moving in the channel because of the powerful electric field might gain too much kinetic energy, get too hot and break into the gate oxide where it wreaks havoc. So we create more lightly doped areas next to the source drain. Same dopants, just less of them. These extensions mean that charge carriers move from source to drain more gradually, like on ramps or off ramps or highways, rather than catapults or something. Making the extensions also necessitates that we produce these oxide spacers attached to the side walls of the dummy gate. This will be addressed as well. We will build the extensions first, then the halos. Then this needs to be done twice, first for the nmos, then the PMOS transistors. It begins again with lithography, another set of photoresist exposure and development steps to seal away the PMOS area under the photoresist layer and ensure that only the NMOS area gets treated. An ion implanter first fires phosphorus atoms into the NMoS's P type silicon well to create the extensions. Then boron atoms are fired at an angle under the gate to create the halos. As with the last time we ran the ion implanter, we we use secondary ion mass spectrometry or sims to measure whether our work was up to spec. Once the NMOS is done, we flip it over and do it again for the PMOS side. We Strip the resist and then do lithography to cover up the NMOS areas and expose the PMOs areas. Then we run the same thing as before, creating the extensions and halos. But since we are doing PMOS now, we flip it. First implant boron atoms to create the source drain extensions and then phosphorus to create the halos, Measure things with the sims, and then strip off the resist with another round of oxygen plasma ashing. Whew. Are we done yet? No, of course not. We haven't finished the spacers for the extensions, but we're making good progress. The dummy gate is up on top of the gate oxide. The source and drain are being defined. We're almost halfway there. Earlier, I made a brief mention of strained silicon, and you might have thought that was it, wasn't it? No way. Strained silicon refers to layers of silicon where the silicon atoms have been stretched a bit further beyond what they're normally used to. Like cotton fabric pulled apart, strain changes the silicon's atomic structure. Charge carriers can travel faster and experience less obstacles, I.e. scattering through strain silicon than relaxed silicon. So you get a 35% speed or 25% power consumption boost without needing to shrink the transistor. This is somewhat complicated. Strain engineering is a whole discipline that exists in the semiconductor world. But roughly speaking, we need to add different types of strained silicon to the PMOS and NMOS transistors. NMOS transistors move electrons, so we stretch out the silicon in order to get our boosts. Tensile strain. This is done by adding a capping layer of silicon nitride over the transistor, which exerts vertical compressive strain down onto the silicon channel, which then spreads out like a gel cushion when your big butt plops down on it. Voila. Tensile strain. We can tune the strain using radio frequency. This layer of silicon nitride is referred to as a contact etch, stop layer or sessile, because it also acts as a stopping layer when we start etching the contacts. Since it also does tensile stuff. We call this the T Cecil PMOs. Transistors, on the other hand, move electron holes. So we need to actually compress the silicon in the channel. Compressive strain. How are we going to get this? Intel pioneered the method of putting silicon germanium in trenches in the source and drain on both sides of the channel. Why? Silicon germanium? It has a lattice match with pure silicon, but a wider lattice structure. So when deposited, the silicon matches the silicon germanium, but is then pushed inwards. Let us start with this one. The PMOS Is quite difficult. And it takes three conceptual steps to pull off. First, we apply the aforementioned spacers of oxides to the dummy gate sidewall and finish off the extensions. This requires us to bring back our old friend Teos cbd. It deposits a layer of silicon nitride a few hundred nanometers across the whole landscape. But now we have silicon nitride on everything. We only want it on the side walls of the dummy gate. So everything else must be etched away. But leaving the side wall layers intact. Meaning that we can only etch in one direction down. In industry parlance, that's an anisotropic etch and back then reactive ion etch with a fluorine based gas was the best tool for the job. Now that is done, the second step. We must etch trenches into the silicon around the dummy gate of the PMOs to make room for the silicon germanium. And this is somewhat challenging. It starts with using thermal oxidation to grow another layer of silicon dioxide over both the NMOs and PMOs. The silicon dioxide serves as a hard mask for more protection for the nmos while we work on the pmos. We then use lithography to cover up the nmos and expose pmos. So you know the drill spin coat with photoresist. Put the wafer into the exposure machine and then develop the latent image. After that, another round of anisotropic reactive ion etch to etch into the hardmask and expose just the PMOS source and drain which are made of doped single crystal silicon plus the top of the dummy gate. Next, the photoresist is stripped off with oxygen plasma ashing. A wet etched step can now dig the trenches around the gate. Why am I reminded of drilling a tooth for a cavity? In the third and last step of this quest, we deposit the silicon germanium. They colloquially call it siga in the industry. Into that carved out trench cavity. This deposition is done using a special CVD called epitaxy. Epitaxy means above in an ordered manner in Greek. And that hints to what is special about it. It grows an ordered crystal structure on top of the substrate. When done right, the epitaxial siga layer latches to the silicon and where its wider atomic structure affects strain. Kind of like braces for teeth. The end result is that compressive strain silicon. We need to get improved electron hole mobility. Finally, we need to turn on the transistor sources and drains making them electrically active. We remove the hard mask and then do lithography to cover up the NMOs. We then use ion Implantation to fire P type dopants like arsenic or boron atoms and at the siga source and drain to make them electrically active. After stripping the photoresist with oxygen plasma ashing, we run the wafer through an annealing step, so shoving it into a furnace and letting it rip at 1000 degrees Celsius. This activates the dopants and also repairs any damage to the crystal structure done by the ion implantation. This high heat is why we do the dummy gate. The real 45nm gate is made from metal and would literally melt at those temperatures. But polysilicon's melting point is 1414 degrees Celsius, so it survives. Next up, we are starting to deal with the contacts. The transistor is coming together. Don't worry about the NMOs, we will get to it later. As I mentioned way earlier, the transistor is wired up to to the interconnect network and the points where these wires make contact with the transistor are called contacts. The issue is that doped silicon and polysilicon are fairly electrically resistive, which slows down performance and generates excess heat. As transistors shrank, their interconnects and contacts shrank too, which makes the resistance even worse. When the interconnects got to be below 1 micrometer wide, the resistance value got too high to be ignored. The IC FAB engineers rummaged around in history for a solution and found that in the 1960s they used platinum silicon alloys to ameliorate resistance in the contacts of diodes. So in the 1980s, the Fabs started depositing thin layers of metal on top of the silicon and alloyed them together with high heat to create a metal silicon alloy layer on top of the source drain. These alloys are called silicides. At first, this was done via a method called polyside, depositing layers of polysilicon and metal over the whole thing, annealing them to create the alloy and then patterning away whatever was unnecessary. Patterning means lithography, however, and that is expensive. In the early 1990s, Fabs introduced a clever method that did not need lithography, meaning it was self aligned. Self aligned silicide shortens to silicide, which sounds dodgy, but so it goes. There are a number of salicide methods because they depend on the particular metal, titanium, nickel or cobalt. We prepare by first cleaning the wafer, depositing another silicon dioxide hard mask. Using lithography to cover up the transistor and etching through the hard mask to expose the source and drain, we deposit a Layer of one of the three aforementioned metals, titanium, nickel or cobalt, over the wafer using a deposition method called sputtering. Depending on the metal I, a capping layer might be also applied to protect it from oxidization. Titanium doesn't need it, but cobalt does. Our particular process flow shows the titanium way. The titanium silicides have a two step formation method which is quite famous. I mean famous in the semiconductor world. Nothing like K pop demon hunters. By the time of the 45 nanometer node, the the fabs are already moving on to cobalt and nickel. But titanium is still good for illustrating what is going on overall. So anyway, after layering the titanium, we do a first annealing at 600 to 700 degrees Celsius wherever the titanium touches silicon. So at the surface of the source and drains, the annealing turns it into an intermediate silicide product called C49. C49's resistivity is still too high to make it usable as a silicide. But it is stable enough to let us remove the unreacted titanium metal with a selective wet etch chemical bath of hydrofluoric acid. This trait of being sensitive to wet etch was not accidental. It is one of the major reasons why these metals were chosen. This step helps avoid producing silicide on unintended areas of the transistor which can cause electrical failures. After removing the unneeded titanium, we do the second annealing step at higher temperatures of 700 to 900 degrees. 850 for short time seems to work the best to turn the C49 intermediate into the final C54 material. CE54 is far more stable and has much less resistance. It's what we want. Now we get back to strain engineering and finish off the NMOS transistor. If you recall from earlier, I mentioned that the way we applied strain to the NMOS silicon was with a dual purpose capping layer called the tensile CECL or T cecal. If you were on edge wondering when we were going to put on the T cecil, you can unclench. Now CVD is used to apply a layer of silicon nitride about 5-30nm on top of both transistors. Now we start to prepare for the interconnect metal layers to be deposited over and connected to the transistors. This begins with the laying down of what is called an interlayer dielectric, or ild as the name implies. Interlayer dielectric insulates and separates the device and metal layers. Here we lay down a few hundred nanometers of silicon dioxide using low pressure CBD or something similar. And finally planarize it with chemical mechanical polishing, grinding all the way down the surface until the dummy gate is exposed. Now the dummy gate is ready to be removed and replaced. With the polysilicon gate exposed, we can remove it with a simple wet etch step. Instead of acid this time, a powerful alkaline is used. Tetramethyl ammonium hydroxide, along with ultrasonic treatment to scrub away every last bit. After the gate's been removed, we can build the real metal gate stack. This consists of the metal gate itself, which here is made of aluminium. But first we need to lay down another layer of metal called the work function metal. The choice of work function metal helps fine tune the PMOS and NMOS transistors. Threshold voltage, meaning the minimum gate voltage that activates the transistor. A lower threshold voltage helps it switch faster, but eats more power via leakage. A higher threshold voltage means slower switch speed, but saves power. So designers tuned the threshold voltage to balance speed against performance. You can guess what intel wanted in those days. Unfortunately for our health and sanity, the PMOS and NMOS Transistors in the 45nm node use different work function metals for the tuning. We need to apply them in a specific sequence to get the desired effect. Simply speaking. Just kidding. None of this is simple at all. This is achieved by first adding a layer of the PMOS work function metal, probably titanium nitride, to both the NMOS and PMOS transistors. Then we use a patterning lithography step to cover up the PMOS and remove the titanium nitride layer that was just deposited out of the NMOS area, essentially resetting it. After removing the photoresist, they then add the NMOS work function metal, probably titanium alumini or titanium aluminium nitride, over both the NMOS and PMOS transistors. Again, I believe that this flow follows that of Intel's first generation 45 nanometer Penrin node presented in late 2007. They later tweaked this in their second generation high K metal gate. Last process flow released in 2008. And I won't go into those tweaks. After depositing the work function metal stacks, we can now produce the metal gate. Intel used simple aluminium to make the gate applied, presumably with some form of cvd. I have also seen tungsten used in some node variants. There is excess aluminium after this, so C and P is used to polish down the unwanted aluminum and complete the metal gate. The gate is done. The Final two things to do now are to make the plugs and copper interconnects. The plugs refer to the vertical pins that go down to the contacts on the transistor, connecting them to the interconnect metal layers. If the transistors are the streets and the interconnects are the highways, then plugs are like the on ramps. I know I use the same metaphor twice. Plugs begin with two layers. First, a layer of silicon nitride deposited via CBD to serve as the stopping layer to keep a future etch process from going too far. Second, we lay down more silicon dioxide to serve as the interlayer dielectric and electrically isolate the gates from the contacts at the source and drain. A lithography patterning step is run to identify where the contacts will be. Then we etch down through the silicon dioxide and silicon nitride layers using powerful trifluoromethane gas and reactive ion etch. The plugs are made from tungsten metal, but first we have to apply a layer of titanium nitride using CVD over the surface and the contact's opening. It will act like a glue layer to keep the tungsten inside the plug and prevent it from dissipating into the silicon. Once that has been applied, we can now fill the plug with tungsten. This was done using a tungsten hexafluoride CVD to cover the whole landscape. Progress on the tungsten films is measured using the aforementioned spectroscopy ellipsometry. But the only way to look into the plugs themselves is with an electron microscope, which means it has to happen off the line anyway. Once the tungsten is applied, we use CMP to polish it all the way back down to the silicon dioxide ILD layer. Progress is good. The plugs and contacts are done, and we are now ready for the first interconnect metal layer. The copper interconnects were the key technology for the 130 nanometer node, and it was famously introduced by IBM in the 1990s as a replacement for aluminum, which historically had been used for making interconnects. But over the years, those aluminum interconnects had gotten too small and resistive to send signals at high speeds. But copper necessitated a redo of how they made interconnects. We produced aluminium metal layers in a subtractive manner, so depositing a blanket aluminium layer, patterning the wires using photolithography, and then dry etching away the excess. Subtractive methods work great, but are incompatible with copper because the pesky metal diffuses into stuff. So IBM and others switched from a subtractive to an additive process inspired by how they once made high end circuit boards. We're in the end game now, so let's finish strong. The damascene method as done for the 45nm node involves first laying down another interlayer dielectric layer or ild. This is done using plasma enhanced cbd. The material differs from the silicon dioxide ILD below at the transistor level. This is made from a special material called Locay dielectric, chosen for having a lower dielectric constant than silicon dioxide. To reduce capacitance issues. I covered the dramatic story of the locate dielectric race in a prior video, one of my personal favorites. A common early choice for the dielectric is fluorine doped silicon glass or fsg. Essentially silicon dioxide doped with fluorine atoms. The later technology generations used carbon doped oxide or porous silicon oxycarbide. Yes, it literally has pores. Once the dielectric layer is laid down, we send this puppy back to the fab's lithography bay and pattern the interconnected network into the ILD layer. We then etch into the dielectric layer using rie, leaving behind a network of deep trenches. The photoresist is stripped off with oxygen plasma ashing. Then we line the trenches with a copper diffusion barrier usually made from tantalum plus a seed layer of copper. This seed layer will be the base for the real copper filled method. Copper electroplating, a wet deposition process that uses an electric current to make thin copper layers. Electroplating has long been known. What IBM learned, and this was their big secret for a time, is that under the right conditions you get this phenomena they dubbed superfill. With superfill, the copper fills the interconnect trench from the bottom up without voids or defects like we might get with other methods like CVD or pvd. Electroplating covers the whole surface with copper. So we need to use CMP to grind away the excess copper and leave behind our completed metal layer of interconnect trenches filled with high quality copper. We're done. Further steps will include more metal layers stacked on top produced with depositing an ILD layer patterning with lithography etched with an anastropic edge and more copper interconnecting. But otherwise we're done. Rejoice. Lord, I did not expect this to be this long or hard. And I don't know how many people survived to the end of this. And just reminding you this was leading edge 18 years ago. A few final thoughts that strike me Sometimes a more advanced process node requires a major change in the flow. Shuffling the steps around. For instance, Intel's 130nm node does well formation before shallow trench isolation. By leaving that out, it seems like a more advanced process node gets better by tightening the tolerances in the steps rather than changing out the steps themselves. Another thought. I cannot imagine how it is to create this process flow, just following it and imagining all the cross effects and reasons why they did it that way. The R and D people who work on this are literal wizards. And lastly, there are so many things that I did not get to things covered in prior videos but not touched upon here. Finfets, gate all around Transistors, photoresist Mask Making, Regular packaging, Advanced Packaging Assembly Inspection test Moving to categories outside of Digital Silicon Carbide, Gallium nitride, power, semiconductors, DRAM, NAND, 3D, NAND, MEMS, radio frequency. All of this just off the top of my head. The wonders of the semiconductor world. There is always so much more. All right everyone, that's it for tonight. Thanks for watching. Subscribe to the channel, Sign up for the Patreon and I'll see you guys next time.