Asianometry Podcast Summary
Episode: The Most Scalable Semiconductor
Host: Jon Y
Date: September 14, 2025

Episode Overview

This episode delves into the remarkable scalability of 3D NAND, a form of non-volatile flash memory that has radically transformed the semiconductor industry. Host Jon Y unpacks the journey from traditional 2D architectures to the innovative 3D designs that have enabled unprecedented density and cost-efficiency in solid-state storage. The episode weaves together technical explanations, market dynamics, and key technological breakthroughs, making sense of why 3D NAND may be the most scalable semiconductor ever mass produced.

Key Discussion Points & Insights

1. NAND Flash: The Starting Point (00:02–04:45)

• Basics of NAND: Jon describes NAND cells as transistors with a unique floating gate, isolated by oxide, that stores charge via quantum tunneling—"isolated like a brain in a vat, screaming into the void, just like me." (02:03)
• 2D vs. NOR: Early dominance of 2D NAND over NOR due to denser, more cost-effective architecture, leading to the rise of solid-state storage. Notably, Apple's adoption in iPods sparked market growth.
• Industry Dynamics: Reflects on the "booms and busts" of the NAND industry, emphasizing constant R&D and intense capital investment to stay competitive.

2. The End of 2D Scaling & Technical Limits (04:45–10:40)

• Scaling Levers and Their Limits: Cost per bit historically improved via Moore’s law (shrinking cells) and multi-level cells (storing more bits per cell).
  • In 1995: 470nm process → 32Mb chips.
  • ~2014: 16nm process → 128Gb chips.
• Diminishing Returns: Smaller cells brought more noise and interference; “losing just 10 electrons materially affects the cell’s contents.” (08:45)
• Industry Consolidation: Technical challenges and downturns slashed the number of NAND makers from 9 to 5 by 2014.

3. The Leap: From 2D to 3D NAND (10:41–19:20)

• Why 2D Was Running Out: Insurmountable patterning costs and cell interference forced companies to rethink architecture—“If we can't grow bit density by shrinking the cells, then let's grow it by stacking more cells on top of each other.” (11:05)
• 3D NAND’s First Approaches: Early 3D attempts literally stacked 2D layers—likened to “building a multi-story Asian mall”—but suffered from increased complexity, heat, and diminishing returns.

4. The Breakthrough—Toshiba’s BICS Architecture (19:21–25:40)

• ‘BitCost Scalable’ (BICS) Process:
  • Invented by Toshiba in 2007, uses a “stack, punch, and plug” method: stacks layers, etches vertical shafts, inserts charge trap layers.
  • Swaps the floating gate for the charge trap—“A charge trap stores electrons like how a sponge stores water trapped in discrete areas inside the materials pores.” (23:27)
• Why Charge Traps?: Simpler manufacturing—"Because the charge trap holds electrons at discrete locations, the fabs can just focus on depositing continuous layers... which is quite formidable by the way." (24:48)
• Manufacturing Challenge: Creating consistently thin layers down deep shafts is nontrivial.

5. Process Innovations & Market Race (25:41–34:55)

• Toshiba vs. Samsung:
  • Toshiba used a “gate first” method with polysilicon gates; good for etching but limits speed and reliability.
  • Samsung’s innovation: a “gate last” method, allowing replacement of polysilicon with superior metal gates. Requires a more convoluted process—removing sacrificial layers to insert charge traps and metal gates.
  • "Metal would be a far better gate material than polysilicon. But Toshiba chose polysilicon for a reason. They needed a material through which they could etch both deeply and cleanly." (28:32)
• Samsung’s TCAT Process: The “terabit cell array transistor”—more complex, but enabled faster, more reliable, and denser 3D NAND.
• Market Impact: Samsung's early 3D NAND (24-layer, 2013) wasn't perfect, but the second gen (2014) far outstripped previous 2D densities—“3D NAND took a step back in process node from 16 to 20ish nanometers but still raised density by 3.5 times. That’s incredible.” (33:17)

6. The Layer Race & Manufacturing Challenges (34:56–41:40)

• Current State: Samsung at 400 layers, SK Hynix in the 300s, others in high 200s; projections up to 500–1000 layers.
• The Etch Bottleneck: Making ever-deeper shafts (60:1 aspect ratio) is tough—“As the shaft gets longer, it is harder to get enough of the reactive particles doing the etch down to the bottom ... resulting in weird shapes like a cone or even a spiral.” (39:35)
• Cryogenic Etch: New technique using ultra-cold temperatures (-70 to -196°C) to improve etching precision for tall stacks.

7. Impact and Industry Reflection (41:41–end)

• NAND’s Place: NAND can’t replace DRAM—“DRAM is just faster and does not wear out”—but NAND is eclipsing hard drives in density growth.
• Incredible Scaling: In a decade, density soared from 2.6 to up to 28 gigabits per square millimeter.
• Industry Envy: “The rest of the semiconductor industry... must be overflowing with envy. They must be thinking, how can we get that scaling trend for ourselves?” (43:50)

Notable Quotes & Moments

• [02:03] Jon: “For all intents and purposes, isolated like a brain in a vat, screaming into the void, just like me.”
• [08:45] Jon: “Now, losing just 10 electrons materially affects the cell's contents.”
• [11:05] Jon: “If we can't grow bit density by shrinking the cells, then let's grow it by stacking more cells on top of each other.”
• [23:27] Jon: “A charge trap stores electrons like how a sponge stores water trapped in discrete areas inside the materials pores.”
• [24:48] Jon: “Because the charge trap holds electrons at discrete locations, the fabs can just focus on depositing continuous layers... which is quite formidable by the way.”
• [28:32] Jon: “Metal would be a far better gate material than polysilicon. But Toshiba chose polysilicon for a reason. They needed a material through which they could etch both deeply and cleanly.”
• [33:17] Jon: “3D NAND took a step back in process node from 16 to 20ish nanometers but still raised density by 3.5 times. That’s incredible.”
• [39:35] Jon: “As the shaft gets longer, it is harder to get enough of the reactive particles doing the etch down to the bottom of the shaft, resulting in weird shapes like a cone or even a spiral.”
• [43:50] Jon: “The rest of the semiconductor industry... must be overflowing with envy. They must be thinking, how can we get that scaling trend for ourselves?”

Timeline of Important Segments

| Timestamp | Topic | |-----------|--------------------------------------------| | 00:02 | NAND fundamentals & early history | | 04:45 | 2D NAND scaling limits & market dynamics | | 10:41 | The motivation for 3D NAND | | 19:21 | Toshiba’s breakthrough BICS architecture | | 25:41 | Samsung’s TCAT & the process race | | 34:56 | The shift to extreme stacking, >300 layers | | 39:35 | Cryogenic etch and manufacturing hurdles | | 41:41 | Industry impact and future prospects |

Conclusion

Jon Y’s deep dive highlights how 3D NAND’s vertical scaling unlocked a new era for memory storage, shifting the cost-performance curve and catalyzing a global tech arms race. From clever materials science to process innovations and cutthroat industry shifts, this episode peels back the complex layers—literally and figuratively—behind the memory inside everything from smartphones to data centers.