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DRAM long ago hit the slow curve of lateral scaling. The only real way left for big bit density gains is stacking up. In a previous video I discussed 3D NAND, the most scalable semiconductor. 3D NAND sparked a scaling revolution in the industry. Can it do the same for dram? But stacking DRAM cells, not dies, is not as easy as stacking NAND cells. In today's video, we talk true 3D dram. This video is brought to you by the Asynometry Patreon. A DRAM cell still has the same iconic structure. One transistor and one storage capacitor. The transistor acts like a gate that can open to allow a current in or out the storage capacitor. The capacitor is a cylinder like structure that retains this charge. It only holds it for a short period of time, so it needs to be constantly refreshed. DRAM cells are connected to two a word line and a bit line. The word line connects to the cell's access transistor's gate so it can turn them on or off. The bit line connects to the capacitor through the axis transistor and it is the path a charge can come in or out of the whole DRAM cell. If we want to increase bit density, then we have to stuff more DRAM cells onto the same piece of silicon, which means scaling down the DRAM cell's size. But making a smaller capacitor means less capacitance, which has trade offs. Lower capacitance makes it harder to sense how the charge changes the voltage on the bit line. And after it comes out of the DRAM cell's capacitor. It also shortens the amount of time the capacitor can hold on to the charge. So we must refresh the DRAM cells faster and more frequently. This is a power suck. Such technology challenges have to be overcome while also keeping the production costs low. Because in the end, companies like Samsung and SK Hynix sell a commodity and with a fluctuating market price, no point in making a dense or high performance DRAM if it costs too much. Let's quickly review the major technology updates in DRAM scaling in the past few decades. In the 2000s, vendors ditched traditional planar capacitors for 3D capacitors. Trench and stacked trench capacitors are etched down into the substrate with the transistor on top. So first the trench is dug out and filled in with materials to make the capacitor. The transistor is made. After that, stacked capacitors by contrast, are built on top of their axis transistors, so the transistor is made first, capacitor second. While trench capacitors gained traction early on, stacked capacitors became more widely used after the capacitors adopted high K metal dielectrics to retain high capacitance. Since these dielectrics are heat sensitive, we must do transistor first, capacitor second. So stacked it is. Two recent major technology transitions for the DRAM industry has been uv and the 4F squared cell. The simplest, though not always cheapest, way to do a shrink is just to print this feature. Smaller lithography helps us print smaller capacitor holes or cuts down on the number of mass steps, which saves money. It also enables new structures like a honeycomb or staggered array. The imminent next step comes at the cell design level. Since 2007, DRAM cells used a layout called 6F squared, where F means the node's minimum feature size or half pitch. A 6F squared cell is set up has a 2F by 3F area, making it more tightly packed than an older 8F squared cell. So 4F squared is what comes next, 2F by 2F, offering a 33% design shrink. The big change here is to make the access transistor a vertical gate type transistor and moving it right underneath the capacitor. The bit line and wordlines are also reduced in size. While the 4F square design saves space, its cells are also harder to make. For instance, the vertical gate transistor's channels are not physically connected to the main bulk silicon substrate. This makes them susceptible to something called the floating body effect. This is where charge slowly accumulates inside the transistor, creating an accidental voltage which which causes the capacitor to leak information. So DRAM continues to physically shrink, but gains are slow and what comes next is unclear. LAM research projects that there will be no more gains when the area per bit reaches about 1000 square nanometers. So about 32 by 32 nanometers. The industry is predicted to hit this density sometime in 2029 or for 2030. After that, who knows? This is why people have started to seriously consider stackable 3D NAND like DRAM. In one fashion, we are already doing 3D DRAM in the form of high bandwidth memory or HBM. HBM stacks a bunch of DRAM dies on top of one another and connects them with vertical channels called through silicon vias. But this stacking is done at the die level using advanced packaging techniques like wafer bonding, which is not quite how 3d nand does nand the NAND industry once faced the same physical scaling issues with planar. After several generations, flash memory cells got so small that 1 they were too difficult to manufacture and 2 their floating gates held so few electrons. So to cause variability errors with 3D NAND, manufacturers step back to a larger, more reliable flash memory cell. But more than compensate for that loss in bit density with huge vertical stacks. To make 3D NAND, we first deposit dozens of alternating layers of dielectric. Then we pattern and punch deep channels through those layers and produce charge traps inside those channels. Each layer becomes a memory cell. The hard expensive stuff, lithography, etch, channel filling, etc. Is done as single steps. So whether The NAND has 1, 3, 5 or even 50 layers, we only need to do that hard lithography, etching, whatever stuff only wants. There are caveats to that of course, but that's the gist of the issue. This is how we can so suddenly get 3D NAND stacks 100, 200, even 300 layers high. There is not a lot of information about what post 4F square 3D DRAM will actually be like, but what is available seems to imply that the major challenge is figuring out what to do with the capacitor. In conventional dram, we have a vertical cylinder shaped capacitor that is tall and skinny, just like how I like my trees. But this tall and skinny capacitor makes each layer too thick to stack upright in meaningful numbers. So how about just knocking these tall and skinny capacitors over onto their side to get horizontal capacitors? This intuitive concept preserves familiarity with the old paradigm, always a plus in the super conservative semiconductor industry. But it is not so easy to just do that. Benjamin Vinson of Lam Research explored the possibility in a thoughtful 2023 blog post and noted several manufacturing challenges. Producing these horizontal capacitors involved first depositing the silicon layers and etching them laterally, meaning sideways to varying lengths, then finally uniformly filling those holes with materials, hopefully in a single action. The issue is that existing techniques are better at etching down than laterally. Etch is about sending reactants deep into a cavity and letting them react with the substrate in the desired direction. Reactants are harder to control when that cavity is lateral, not vertical. The same goes for deposition, so just flipping the structure on its side will be a nightmare and we should avoid it like Freddy Krueger. For these reasons, the capacitors cannot get as horizontally long as they are tall. Today, modern DRAM capacitors can be 1, 2, or even 3 micrometers deep, which is kind of wild considering they're just 20 to 30 nanometers wide. We can't etch 3 micrometers laterally, so the horizontal capacitors will be shorter, making them less effective. Third, there will be issues reaching and connecting the various word lines and bitlines. The sideways area is just too dense to produce all this. So all in all, the sideways method is not going to work. So Vincent and his team at LAM used the process simulator called Cemulator 3D to redesign the architecture. They first made the capacitor short and wide, rather than tall and skinny. Capacitance is proportional to the capacitor's surface area, so a short and wide capacitor can theoretically offer something as good as tall and skinny. To create more space for the capacitors, the bit lines are moved over to the end of the whole sheet structure. The this lets us make a bitline trunk that is shared between two opposing sheets. LAM also made the axis transistors gate all around transistors. These are leading edge structures that do a better job of controlling the current. This helps retain gating performance. The architecture that they ended up with kind of looks like a strange Lego pine tree. Or this one building in Taipei's Nehu district that I bike passed a lot. I've seen several 3D dram designs that are kind of like what Vincent cooked up. Short and wide horizontal capacitors sticking out like leaves. They generally seem to be referred to as horizontal capacitor or horizontal nanosheet. One major difference between these designs is where to place the bitlines and word lines. First, you have a category with a vertical bitline. That vertical bitline runs through the many layers, leaving a horizontal wordline that stays within each layer. Second, there is a vertical wordline category with a horizontal bitline. So the inverse. Each category has their own tradeoffs. Broadly speaking, industry people seem to hint that vertical bitline efforts offer more promise. A smaller physical footprint, and the bitline goes direct to the peripheral CMOS circuits. But we are not yet in full production, so things remain outstanding. We know that DRAM makers are working on variants of this, so let me cite a few examples. Micron in particular, if it works for them, 3D stacking would let them produce higher capacities without spending as much. It fits their mo, which tends to optimize for cost. They have been filing patents on horizontally oriented DRAM cells for over a decade now. Key issues have been ensuring that the axis transistor and capacitor still perform as expected when billions of them are stacked on top of each other. The Korean press, for obvious reasons, keeps close tabs on Micron technology. Many rumors fly about, but Micron themselves have not said anything about such a breakthrough. If Micron is working on it, then you can be sure that Samsung and SK Hynix are as well. In May 2024 a Samsung EVP reported at a conference that they completed a 16 stack 3D dram which they called then Vertically Stacked Cell Array Transistor or VSCAT style. That Samsung EVP also apparently said that Micron had made it up to an 8 layer 3D DRAM stack, though I must note that I haven't seen any other sources on this. The ELEC reports that VSCAT would use wafer bonding in some form to bond the memory cell wafers to the wafer with the peripheral CMOS support circuits. Apparently the two are difficult to produce together on the same wafer. So far as I can tell, Samsung would later rebrand VSCAT to Vertically Stacked DRAM or VS dram. I think this new name at least makes a bit more sense than the old one. China's flagship dram maker, Cxmt is also working on 3D dram. In March 2026 they published a paper discussing a five layer 3D dram that they produced. Interestingly enough, it uses a vertical wordline which rather than a vertical bit line. They also hinted a 64 layer test vehicle fabbed just to test some of the processes. Pretty cool. But that's not a real device. Okay, big brain time. So if the capacitor keeps creating problems with 3D dram, why not get rid of it altogether? This is the idea behind the next capacitorless 3D dram. Yes, I know. Can we still call it a DRAM memory if it no longer has the capacitor? What would Robert Dennard think? But here we are and actually the idea of capacitorless memory has been around for a while. One proposal that gained some noise was floating body DRAM which utilized the aforementioned floating body effect to store a charge inside a silicon on insulator transistor. Another concept called A2 RAM worked similarly. In principle these two work, but their performance is not all that robust. In some cases they are quite delicate and not that practical. So few of these capacitorless drams gained real traction until 2020 when a concept emerged using an oxide semiconductor called Indium Gallium Oxygen zinc oxide or Igzo. Igzo was first discovered in 2004 in Tokyo. It was commercialized in the early 2000 and tens by Sharp to produce these thin film transistors placed inside the backplanes of screens. Such IGZO transistors are today still used in flexible displays and panels. The material is known for its amorphous structure, transparency and ultra low leakage when turned off. This latter part is critical for making this all work anyway. In 2020, a team led by IMEC researcher Atelio Belmonte published a paper proposing the IGZO 2T0C DRAM cell which replaced the one capacitor and one transistor with two thin film IGZO transistors. The concept is a twist on an older embedded memories design called two transistor gain cell memory. What makes this thing so clever is how it uses one of the two transistors as the capacitor. The memory cell is made up of two transistors wired together. One transistor is for reading and the other is for writing. When the write transistor turns on, a charge flows into the gate of the read transistor. The read transistor's gate has the structure of a capacitor which allows it to store that charge via parasitic capacitance. To read the cell, we run a small read current through the read transistor. The presence of a charge inside that read transistor's gate will create an electric field that changes the conductivity of of the transistor channel. Ergo, if the current flowing through is large, then the stored bit is probably a 1. If it is low or practically zero, then the bit is probably zero. Note that this read action is non destructive which is different than with dram. These gain cell designs didn't work too well when implemented in silicon because silicon transistors are fairly leaky. But igzo's high bandgap and virtually zero leakage makes the IMEC design far more feasible. That ultra low leakage also means longer data retention times, some cases as long as 400 seconds or a thousand times longer than regular dram. Imec also notes that the transistor can scale down to 14nm long without sacrificing much retention. So what is the catch or catches? One is that we will need lots of contacts and interconnects to connect the read and write transistors. While we can optimize this, this likely makes the cells larger. Some papers say you need a 9F squared cell quite large. And while IGZO films being relatively easy to deposit makes their transistors more stackable and the cell is not totally flat Irregular bumps due to all the interconnects and contacts can make it complex to build up large stacks. Another is reliability. Traditional DRAM cells can work for many millions of cycles, but the two T0C's capacitor gate gate is small and fragile. It is susceptible to manufacturing defects and outside effects that can cause the transistor's performance to shift over over time. One serious issue is called positive bias temperature instability or pbti, when a constant electric field at elevated temperature traps electrons in or near the transistor's gate oxide. This shifts the transistor's threshold voltage, thus altering our ability to properly read its bit. In the context of 3D drams, being stuffed into a big stack means mechanical stress and higher temperatures. Research has found that both only worsen the threshold voltage shift via PBTI. Nevertheless, the 2020 IMIC paper triggered a flood of new research across the world and IGZO has been added to various long range roadmaps relating to the DRAM industry. That does not mean it is going to make it to fab floors. There exist other competing concepts, including an intriguing one that uses dyristors, but IGZO is a serious contender since these stackable options are not yet quite ready for primetime. The current situation is to stack more DRAM dies a la HBM and advanced packaging. Bringing NAND's scalability trick over to DRAM would be revolutionary, but it won't be easy. NAND memory is a bulk NAND non volatile storage, so fabs compete to get the cheapest, densest memory possible so they can sell at the lowest cost per stored bit rate. DRAM on the other hand, is a working memory. For GPUs and CPUs there are necessary requirements other than just pure storage space like very fast random access, the ability to survive unlimited rewrites without wearing down and low leakage. But progress is being made and I dare say we will soon see true 3D dram, hopefully by the end of the decade. Alright everyone, that's it for tonight. Thanks for watching. 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