Your phone, watch, and even your fridge want real-time intelligence—but power and latency won’t tolerate bloated models or generic compute. We walk through a practical path from Python to custom hardware using high-level synthesis, then invite you to prove it in our Efficient Inferencing Hackathon. With a ready-to-run RISC‑V Rocket Core baseline for MNIST, a full Siemens EDA toolchain, and on-demand training, you’ll learn how to cut latency and power while protecting accuracy through precision mapping, parallelism, and smarter dataflow.

We start by mapping the compute landscape—CPUs for flexibility, GPUs for throughput, TPUs/NPUs for tensors, and custom FPGA/ASIC designs for peak power-performance-area. From there, we get tactical: use quantization to right-size bit-widths; apply loop pipelining and unrolling to unlock throughput; partition memories and stream between layers to eliminate round-trips; and iterate quickly with HLS directives instead of rewriting RTL. You’ll see how a baseline inference in the millisecond range can be driven far lower with disciplined co-design, and how Catapult HLS, Questa, and PowerPro provide the feedback loop—latency, area, and power—to make confident trade-offs.

Participants receive a virtual machine, C kernels for convolution and dense layers, and a step-by-step path from Keras to synthesizable RTL. The goal is simple and demanding: deliver the fastest MNIST implementation that meets accuracy, area, and energy targets. Along the way, the HLS Academy community offers guidance from experts and peers, and winners will be announced at the Edge AI Foundation event in Taipei, with prizes including a 3D printer, an FPGA board, and Bose earbuds.

Ready to turn models into efficient silicon? Join the workshop series, claim your VM via the QR code at hls.academy, and use the promo code with two underscores to unlock full access. If this resonates, subscribe, share with a teammate who ships edge AI, and leave a review to help others find the show.

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