TestBench:

In Verilog is a predefined sequence of input combinations to observe the response of DUT (Design under Test). It ensures the intent of the design using different types of input vectors.

Need of the Testbench:

Most of the beginners observes the response of their designs by forcing the input vectors manually on the waveform window. For a newbie it is all right to start with this method, but, imagine if you are going to make some large designs means you have now more numbers of the inputs and outputs say around more than 10 then designer will not be able to test the design by simple forcing and making changes again and again. this process can take much longer time to close your design.

To make the design time shorter we use some predefined sequence of the inputs which are connected to the DUT now designer have to run this testbench and observe the desired output response. This method allows debugging simpler and efficient.

The DUT can be a behavioral, gate level or dataflow implementation of any design. Verilog test bench is nothing but a Verilog module. It is helpful when we need to use millions of gates on a single chip. It is also helpful while debugging and helps in debugging fast. It can be written before or after the main module but is executed only after the main module is executed. Test Bench gives designer, the liberty to use a number of inputs and observing their corresponding output in the design at the same time. Also this helps in testing the dynamic behavior of the circuit.

Steps to make a Testbench:

STEP 1: To create a dummy template that declares inputs to the DUT as reg and outputs from the DUT as wires. The module name in this template must be different from that of the main module.

STEP 2: Connecting the DUT with testbench using Instantiation.

STEP 3: Stimulation of input vectors to the DUT.

STEP 4: Displaying the response of the design.

Please visit “www.semiconductorclub.com/blog” to know more about all the steps in depth with example.