Logic Equivalence Check: ASIC design cycle involves a number of stages which varies from functional design to its verification at different levels. As soon as design is completed and verified through different methodologies is ready to go to a semiconductor chip. Hold on, it’s not simple as it said, one of the most crucial step is involved while taking RTL design to the chip level. Synthesis, which involves conversion of RTL design to the equivalent gate level netlist. This netlist is then used for the physical design implementation.

Once the netlist get generated it is must to ensure that its functionality is equivalent to the RTL design from which it has been generated. The logical equivalence check performed to ensure the logical equivalency of the gate level Netlist with the RTL design. It can also be performed to check the equivalence of the:

Netlist to Netlist
library to library

A number of EDA companies provide equivalency check tools out of them Formality (Synopsys) and Conformal (Cadence) and mostly used at industry level...

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